The present invention relates to a clock network for transmitting a clock signal, and more particularly, to a clock tree network provided with a power consumption reduction function.
In a semiconductor integrated circuit device, synchronization circuits including flip-flop circuits may be provided with a clock signal from a clock tree network configured by buffer circuits. The higher integration of recent semiconductor integrated circuit devices has increased the number of buffer circuits in a clock tree network. Due to the demand for lower power consumption of semiconductor integrated circuit devices, the power consumed by a clock network tree must be reduced.
FIG. 1a is a schematic circuit diagram showing a first prior art example of a clock network 100a. The clock network 100a provides a clock signal CLK in parallel to a plurality of flip-flop circuits FF1 to FF4. The clock signal CLK is provided to the flip-flop circuits FF1 to FF4 via a buffer circuit group 1a. 
FIG. 1b is a schematic circuit diagram showing a second prior art example of a clock tree network 100b including a gated clock buffer (GCB), which functions as a transmission control circuit. Flip-flop circuits FF1 and FF2 are provided with a clock signal CLK via a buffer circuit group 1a. Flip-flop circuits FF3 and FF4 are provided with the clock signal CLK via the GCB and a buffer circuit group 1b. 
When there is no need to provide the flip-flop circuits FF3 and FF4 with the clock signal CLK, the GCB interrupts the clock signal CLK provided to the buffer circuit group 1b. This reduces the power consumption of the buffer circuit group 1b. 
Less buffer circuits and a shorter network are effective for reducing the power consumed by the above-described clock tree network. The use of a transistor having a relatively low threshold in each buffer circuit to increase the load driving capacity is also effective. However, a transistor having a relatively low threshold would increase leakage current during inactivation.
FIG. 2 is a schematic circuit diagram showing a third prior art example of a clock network 200 for decreasing leakage current in buffer circuits, which configure the clock network 200. The clock network 200 includes a switch circuit 2, which is connected between a buffer circuit group 1c and a power supply VDD, and a switch circuit 3, which is connected between the buffer circuit group 1c and a power supply VSS. In a standby state, the switch circuit 2 and the switch circuit 3 are disconnected from the power supplies VDD and VSS, respectively. This stops the flow of leakage current from the power supply VDD to the power supply VSS in the standby state.
FIG. 3 is a schematic circuit diagram showing a fourth prior art example of a clock network 300. In the clock network 300, the switch circuit 2 and switch circuit 3 of the clock network 200 are respectively embodied by a P-channel MOS transistor Tr1 and an N-channel MOS transistor Tr2. In the clock network 300, when a buffer circuit group 1c is in a standby state (power save mode), the transistors Tr1 and Tr2 are inactivated to stop the flow of leakage current from the power supply VDD to the power supply VSS.
Due to the miniaturization of semiconductor integrated circuit devices in recent years, when the gate of a transistor is narrowed, the leakage current during inactivation tends to relatively increase. By using the transistors Tr1 and Tr2 having a relatively high threshold, leakage current would be decreased during inactivation. Further, in the buffer circuit group 1c, the use of a transistor having a relatively low threshold would increases the load drive capacity. This would reduce the number of buffer circuits and shorten the network length.
Japanese Laid-Open Patent Publication No. 2000-82286 describes a CMOS circuit connected to a power supply switch including a transistor, which is inactivated during a standby state. Due to the power supply switch, the leakage current produced when the CMOS circuit is in the standby state is only the leakage current produced by a power supply switch including a transistor.